9.1.d Logic Circuit Design with 74155 Decoder configured as a 3-to-8-line Decoder A combinational circuit has three inputs X, Y, Z and two outputs F1 and F2 which are F1=XYZ+X' Y' Z' F2=XYZ'+X Y' Z' i) Design a circuit that generates F1 and F2 using a 74155 decoder and external NAND gates.Ic 74155 Datasheets Context Search Catalog DatasheetĪbstract: IC 74156 74255 74155 demultiplexer 74155 Demultiplexer IC 74155 74155 decoder demul ic 74155 decoder 74156 While you are designing the circuit, draw the 3-to-8-line decoders as blocks. 9.1.b 4-to 16-Line Decoder with dual 3-to 8-Line Decoder Design a 4-to-16-line decoder using two 3-to-8-line decoders. While you are designing the circuit, draw the 2-to-4-line decoders as blocks. FUNCTION TABLES 2-LINE-TO-4-LINE DECODER OR 1-LINE-TO-4-LINE DEMULTIPLEXER OUTPUTS SELECT B A INPUTS STROBE 1G H 1 YO 141 1Y2 1Y3 DATA 1C x X H H H H L L H H H L L H L H H н H L H H H L H L L H H L н L H H H H х H х H н L H X L H H OUTPUTS DATA 2YO 241 2Y2 2Y3 SELECT B A х LL 2C х H н H INPUTS STROBE 2G H L L L L H H L L H H L L H L H H H H L H L H H H H H L H L L н х х X H H H H H Figure 6 Truth Table of the 74155 IC when configured as a dual 2-to-4-line decoder.ĩ.1.a 3-to 8-Line Decoder with dual 2-to 4-Line Decoder Design a 3-to-8-line decoder using two 2-to-4-line decoders. 3-LINE TO-8-LINE DECODER OR 1-LINE-TO-8-LINE DEMULTIPLEXER OUTPUTS (0) (1) (2) (3) (4) (5) (6) (7) INPUTS STROBE SELECT OR DATA ct BA G+ X X X x H LLL L LLH L L LHL L LHH L HLL L HLH L HHL L HHH L 2YO 281 282 2Y3 1YO 1Y1 1Y2 1Y3 H H H H H HH H L н н H H Η Η Η H L н H H Η Η Η H H L H H H н н н H H H L H н н н H H H H L Η Η Η H H H H H ι Η Η н H H H H HL H н H H H H н н L C = inputs 1 C and 2 connected together #G = inputs 1G and 2G connected together H = high level, L = low level, X = irrelevant Figure 5 Truth Table of the 74155 IC when configured as a 3-to-8-line decoder. STROBE (2) 1G 17, OUTPUT 1 YO DATA 1C 16) OUTPUT 1Y1 (5) OUTPUT 1Y2 SELECT (3) B (4) OUTPUT 1Y3 (9) OUTPUT 2Y0 SELECT (13) A (10) OUTPUT 241 DATA (15) 2C (11) OUTPUT 2Y2 STROBE (14) 2G (12) OUTPUT 2Y3 Figure 4 Logic Diagram of the 74155 ICįigure 5 and Figure 6 show the truth tables for the 74155 IC configured as a 3- to-8-line decoder and a dual 2-to-4-line decoder, respectively. Also, the Dual 2-to-4- line Decoder configuration can be seen from the same diagram. GND 8 010 UDDDDDD 16 150 20 140 25 130 A 12 2Y3 11 2Y2 10 9 2 YO 2Y1 Figure 2 Connection Diagram of the 74155 ICįigure 3 shows the Truth Table of the 74155 IC when configured as a 3-to-8-line decoder. 16 Voc 9 1 2YO C1 10 15 291 Х 2 11 282 3 12 Y B 2Y3 74155 7 13 Z 1 YO А 6 2 141 Gi 5 1Y2 14 4 G2 1Y3 GND 8 Figure 1 Schematic Diagram of the 74155 IC configured as a 3-to-8-Line Decoder The Connection Diagram of the 74155 IC is shown in Figure 2. When a 3-to-8-line decoder is desired, inputs C1 and C2 must be connected together as well as input G1 and G2, as shown in Figure 1. Schematic diagram of the 74155 Decoder IC is shown in the Figure 1. The 74155 Decoder IC can be configured as a dual 2-to-4-line decoder or as a single 3-to-8-line decoder.
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